1. Field the Invention
The present invention relates to an A/D (analog-to-digital) converter including a voltage dividing network for dividing a reference voltage into a plurality of arbitrary voltage values, and a plurality of comparators for comparing divided voltage values divided by the voltage dividing network and a voltage value of an analog signal to be input.
2. Description of the Related Art
A technique for digitizing a signal for processing is playing a very significant role today with development of semiconductor devices and computers. With reference to FIG. 1, for example, a satellite broadcasting or the like is carried out as follows. First, an analog video signal is acquired by a TV camera 102, and the acquired analog video signal is then digitized by an A/D converter 104. The digitized video signal is digitally encoded for transmission by an encoder 106, then re-converted into an analog signal by a D/A converter 108 and transmitted to a broadcasting satellite 110. The analog signal repeated by the broadcasting satellite 110 is transmitted again to ground and then re-converted into a digital signal by an A/D converter 112. The digital signal is then subjected to a processing by a decoder 114 opposite to the processing by the encoder 106. The digitized video signal output from the decoder 114 is converted into an analog signal by a D/A converter 116 and then transmitted to a TV monitor 118.
In order to thus digitize the signal, it is necessary to once digitize an input signal obtained as an analog signal by the A/D converters 104 and 112.
FIG. 2 is one example of a ladder resistor array for use in an A/D converter. This ladder resistor array serves to produce a plurality of voltages called reference tap voltages which are to be compared with an input analog signal. With reference to FIG. 2, this ladder resistor array 120 includes a reference voltage terminal 124 connected to a first reference voltage, a reference voltage terminal 126 connected to a second reference voltage, and x ladder resistor cells 122a, 122b, . . . , 122x connected in series between the terminals 124 and 126. Reference tap voltages 1 to x are taken out from connection points of the respective ladder resistor cells 122a, 122b, . . . , 122x. These reference tap voltages 1 to x are compared at predetermined timing with a voltage value of the input analog signal. As the result of the comparison, it can be informed which range of reference tap voltage is lower than the voltage value of the input analog signal. On the basis of this information, it is possible to produce a digital signal representing the voltage value of the input analog signal.
FIG. 3 shows some of comparators and their vicinity of a background art A/D converter. This A/D converter has a resolution of N bits. In order to realize the N-bit resolution, 2.sup.N comparators and 2.sup.N ladder resistor cells are required.
With reference to FIG. 3, this A/D converter includes an analog signal input terminal 128 supplied with an analog signal, a reference voltage terminal 130 connected to a power source of a first reference voltage, a reference voltage terminal 132 connected to a second reference voltage power source different from the first reference voltage power source, a ladder resistor array 140 comprised of 2.sup.N ladder resistor cells and disposed being bent between the reference voltage terminals 130 and 132 for resistance dividing reference voltages produced from a reference voltage 1 and a reference voltage 2, a comparator array 141 including 2.sup.N comparators 142, . . . , 144, provided along the bent ladder resistor array 140, for making a comparison between a voltage value of the analog signal input from the analog signal input terminal 128 and reference tap voltages generated by the ladder resistor array 140, an analog signal line 136 for applying the analog signal input from the analog signal input terminal 128 to each of the comparators included in the comparator array 141, a clock signal input terminal 134 supplied with a clock signal for controlling an operation of each comparator included in the comparator array 141 and sampling an analog signal at predetermined timing, and a clock signal line 138 for applying the clock signal applied form the clock signal input terminal 134 to each comparator of the comparator array 141.
The conventional A/D converter shown in FIG. 3 carries out the following operation. The reference voltage terminal 130 is connected to the first reference voltage power source, and the reference voltage terminal 132 is connected to the second reference voltage power source. The ladder resistor array 140 resistance-divides voltages applied to the reference voltage terminals 130 and 132 and generates 2.sup.N reference tap voltages. Each of the comparators 142, . . . , 144 and the like included in the comparator array 141 compares one of those reference tap voltages with the voltage value of the analog signal. The voltage value of the analog signal is converted into a digital signal on the basis of the result of the comparison by each of the comparators of the comparator array 141.
Conventionally, it has been necessary to bend a comparator array at several places (three places in the case with FIG. 3) for provision of the comparator array as shown in FIG. 3 in relation with a chip size. Accordingly, it has also been necessary to bend the ladder resistor array 140 in the same manner. Thus, there occurs a change in the resistance value of the ladder resistors due to the bending portions as compared to the case where the comparator array is aligned linearly. Consequently, errors occur in the values of reference tap voltages generated by the ladder resistor array. Further, there occurs a line delay in clock signals or the like because of wiring lengths of the signal lines. There is a large difference in the wiring length from the clock signal input terminal 134 between, e.g., the first comparator 142 and the N-th comparator 144, resulting in different timings of the clock signals to be applied. More specifically, the clock signal to be input to the comparator 144 is delayed from the clock signal to be input to the comparator 142.
FIG. 4(b) and (c), show timing charts of clock signals (control signals) PA and PA input to the comparators 142 and 144, respectively.
As shown in FIG. 4(b) and (c), a line delay .DELTA.t occurs between the clock signals PA and PA of the comparator 142 and the clock signals PA and
input to the comparator 144. For comparison of the same analog signal (FIG. 4(a)), the comparators 142 and 144 must compare their reference tap voltages and the voltage value of the analog signal at the same timing. Despite the necessity of the comparison, this line delay causes a deviation in the sampling timings of the comparators 142 and 144, resulting in different values of the analog signal to be sampled, as shown in FIG. 4(a). Therefore, the conventional A/D converter has the disadvantage that a precision in operation is degraded because of such errors of reference tap voltages and such delay of clock signals or the like.